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ltc4259a 1 4259afb controls four independent 48v powered ethernet ports each port includes: ieee 802 ? .3af compliant pd detection and classification output current limit with foldback short-circuit protection with fast gate pull-down pd disconnect using ac or dc sensing power good indication operates autonomously or controlled by i 2 c tm serial interface 4-bit programmable digital address allows control of up to 64 ports programmable int pin eliminates software polling current and duty cycle limits protect external fets available in a 36-pin ssop package quad ieee 802.3af power over ethernet controller with ac disconnect ieee 802.3af compliant endpoint and midspan power sources ip phone systems dte power distribution the ltc ? 4259a is a quad C48v hot swap tm controller designed for use in ieee 802.3af compliant power sourcing equipment (pse). it consists of four independent ports, each with output current limit, short-circuit protec- tion, complete powered device (pd) detection and classi- fication capability, and programmable pd disconnect using ac or dc sensing. used with power mosfets and passives as in figure 1, the ltc4259a can implement a complete ieee 802.3af-compliant pse. the ltc4259a can operate autonomously or be controlled by an i 2 c serial interface. up to 16 ltc4259as may coexist on the same data bus, allowing up to 64 powered ethernet ports to be controlled with only two digital lines. fault con- ditions are optionally signaled with the int pin to eliminate software polling. external power mosfets, current sense resistors and di- odes allow easy scaling of current and power dissipation levels and provide protection against voltage and current spikes and esd events. the ltc4259a is available in a 36-pin ssop package. linear technology also provides solutions for 802.3af pd applications with the ltc4257, ltc4257-1 and ltc4267. figure 1. complete 4-port powered ethernet power source dgnd ad3 rs1 to rs4: 0.5 ? q1 to q4: irfm120a ad2 ad1 ad0 sdaout sdain scl detect4 detect3 detect1 detect2 agnd int C48v v ee shdn1 sense1 r s1 r s2 r s3 r s4 gate1 q1 q2 q3 q4 s1b 4 cmpd3003 4 10k 10k 10k 10k 1k 4 0.47 f 100v 4 x7r port1 port2 port3 port4 4259a f01 smaj58a 4 0.1 f 100v 4 out1 sense2 gate2 ltc4259a out2 sense3 gate3 out3 sense4 gate4 out4 shdn2 shdn3 shdn4 v dd 3.3v 0.1 f auto byp oscin reset 0.1 f 100v x7r 0.1 f features descriptio u applicatio s u typical applicatio u , ltc and lt are registered trademarks of linear technology corporation. hotswap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners.
ltc4259a 2 4259afb supply voltages v dd to dgnd .......................................... C 0.3v to 5v v ee to agnd ......................................... 0.3v to C 70v dgnd to agnd (note 2) .................................... 1v digital pins scl, sdain, sdaout, int, auto, reset shdn n , ad n ................. dgnd C 0.3v to dgnd + 5v analog pins gate n (note 3) ................... v ee C 0.3v to v ee + 12v detect n peak currents (note 4) .................. 80ma sense n ................................. v ee C 0.3v to v ee + 1v out n .................................... v ee C 70v to v ee + 70v oscin .......................... dgnd C 0.3v to dgnd + 5v byp current .................................................... 1ma operating ambient temperature range ltc4259ac ............................................. 0 c to 70 c junction temperature (note 5) ............................ 150 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c order part number t jmax = 150 c, ja = 80 c/w ltc4259acgw (note 1) absolute axi u rati gs w ww u package/order i for atio uu w consult ltc marketing for parts specified with wider operating temperature ranges. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view gw package 36-lead plastic ssop 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 reset byp int scl sdaout sdain ad3 ad2 ad1 ad0 detect1 detect2 detect3 detect4 dgnd v dd shdn1 shdn2 oscin auto out1 gate1 sense1 out2 gate2 sense2 v ee out3 gate3 sense3 out4 gate4 sense4 agnd shdn4 shdn3 electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. agnd = dgnd = 0v, v dd = 3.3v, v ee = 48v unless otherwise noted (note 6). symbol parameter conditions min typ max units power supplies v dd v dd supply voltage 3 3.3 4 v v ee v ee supply voltage to maintain ieee compliant output (note 7) C48 C57 v i dd v dd supply current 2.5 5 ma i ee v ee supply current normal operation C2 C5 ma classification into a short (v detect n = 0v) (note 8) 100 ma v ddmin v dd uvlo voltage 2.7 v v eeminon v ee uvlo voltage (turning on) v ee C agnd C31 v v eeminoff v ee uvlo voltage (turning off) v ee C agnd C28 v detection i det detection current first point, v detect n = C10v 235 300 a second point, v detect n = C3.5v 145 190 a v det detection voltage compliance open circuit, measured at detect n pin C20 C23 v r detmin minimum valid signature resistance 15.2 17 19 k ? r detmax maximum valid signature resistance 26.7 29 33 k ? classification v class classification voltage 0ma < i class < 31ma C16.4 C21 v i class classification current compliance into short (v detect = 0v) 55 75 ma order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
ltc4259a 3 4259afb electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. agnd = dgnd = 0v, v dd = 3.3v, v ee = 48v unless otherwise noted (note 6). symbol parameter conditions min typ max units i tclass classification threshold current class 0-1 5.5 6.5 7.5 ma class 1-2 13 14.5 16 ma class 2-3 21 23 25 ma class 3-4 31 33 35 ma class 4-overcurrent 45 48 51 ma gate driver i gon gate pin current gate on, v gate n = v ee C20 C50 C70 a i goff gate pin current gate off, v gate n = v ee + 5v 30 50 95 a i gpd gate pin short-circuit pull-down v gate n = v ee + 2v 100 ma ? v gate external gate voltage (v gate n C v ee )i gate n = C 1 a (note 3) 10 13 15 v output voltage sense v pg power good threshold voltage v out n C v ee 123 v i vout out pin bias current 0v > v out n > C10v C6 a C10v > v out n > C30v C18 a v out n = C48v C20 a current sense v cut overcurrent detection sense voltage v sense n C v ee , v out n = v ee (note 9) 166 187.5 199 mv v lim current limit sense voltage v sense n C v ee , v out n = v ee 201 212.5 224 mv v sense n C v ee , v out n = agnd C 30v 201 224 mv v sense n C v ee , v out n = agnd C 10v 30.2 mv v min dc disconnect sense voltage v sense n C v ee 2.52 3.75 4.97 mv v sc short-circuit sense voltage 275 mv i sense sense pin bias current v sense n = v ee C50 a ac disconnect (note 10) r oscin input impedance of oscin pin 0.1v < v oscin < 3v, f oscin < 200hz 200 500 k ? a vacd voltage gain oscin to detect1, 2 port powered, pd not present C2.7 C3 C3.3 v/v voltage gain oscin to detect3, 4 port powered, pd not present 2.7 3 3.3 v/v i acdmax ac disconnect detect n output current port powered, C6v < v detect n < 0v 600 a i acdmin remain connected detect pin current port powered, v detect n = C3.4v 150 200 260 a digital interface v old digital output low voltage i sdaout = 3ma, i int = 3ma 0.4 v i sdaout = 5ma, i int = 5ma 0.7 v v ild digital input low voltage scl, sdain, reset, shdn n , auto, ad n 0.8 v v ihd digital input high voltage scl, sdain, reset, shdn n , auto, ad n 2.4 v r pu pull-up resistor to v dd ad n , reset, shdn n 50 k ? r pd pull-down resistor to dgnd auto 50 k ? ac characteristics t detdly detection delay from detect command or application of pd to port 170 590 ms to detect complete t det detection duration time to measure pd signature resistance (figure 2) 170 230 ms t clsdly classification delay from successful detect in auto or semiauto mode 10.1 52 ms to class complete from classify command in manual mode (figure 2) 10.1 420 ms t class classification duration (figure 2) 10.1 13 ms t pon power on delay, auto mode from valid detect to port on in auto mode (figure 2) 130 ms from port on command to gate pin current = i gon 1ms (note 10)
ltc4259a 4 4259afb electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. agnd = dgnd = 0v, v dd = 3.3v, v ee = 48v unless otherwise noted (note 6). symbol parameter conditions min typ max units t start maximum current limit duration during t start1 = 0, t start0 = 0 (figure 3) 50 60 70 ms port start-up t start1 = 0, t start0 = 1 25 30 35 ms t start1 = 1, t start0 = 0 100 120 140 ms t start1 = 1, t start0 = 1 200 240 280 ms t icut maximum current limit duration after t icut1 = 0, t icut0 = 0 (figure 3) 50 60 70 ms port start-up t icut1 = 0, t icut0 = 1 25 30 35 ms t icut1 = 1, t icut0 = 0 100 120 140 ms t icut1 = 1, t icut0 = 1 200 240 280 ms dc clmax maximum current limit duty cycle reg16h = 00h 5.8 6.3 6.7 % t dis disconnect delay t dis1 = 0, t dis0 = 0 (figures 4, 5) 300 360 400 ms t dis1 = 0, t dis0 = 1 75 90 100 ms t dis1 = 1, t dis0 = 0 150 180 200 ms t dis1 = 1, t dis0 = 1 600 720 800 ms t vmin dc disconnect minimum pulse v sense n C v ee > 5mv, v out n = C48v (figure 4) 0.02 1 ms width sensitivity (note 11) i 2 c timing f sclk clock frequency (note 11) 400 khz t 1 bus free time figure 6 (notes 11, 12) 1.3 s t 2 start hold time figure 6 (notes 11, 12) 600 ns t 3 scl low time figure 6 (notes 11, 12) 1.3 s t 4 scl high time figure 6 (notes 11, 12) 600 ns t 5 data hold time figure 6 (notes 11, 12) 150 ns t 6 data set-up time figure 6 (notes 11, 12) 200 ns t 7 start set-up time figure 6 (notes 11, 12) 600 ns t 8 stop set-up time figure 6 (notes 11, 12) 600 ns t r scl, sdain rise time figure 6 (notes 11, 12) 20 300 ns t f scl, sdain fall time figure 6 (notes 11, 12) 20 150 ns t fltint fault present to int pin low (notes 11, 12, 13) 20 150 ns t stopint stop condition to int pin low (notes 11, 12, 13) 60 200 ns t araint ara to int pin high time (notes 11, 12) 20 300 ns note 7: the ltc4259a is designed to maintain a port voltage of C46.6v to C57v. the v ee supply voltage range accounts for the drop across the diode, mosfet and sense resistor. note 8: v ee supply current, while classifying a short, is measured indirectly by measuring the detect n pin current while classifying a short. note 9: the ltc4259a implements overload current detection per ieee 802.3af. the minimum overload current (i cut ) is dependent on port voltage; i cut_min = 15.4w/v port_min . an ieee compliant system using the ltc4259a should maintain port voltage above C46.6v. note 10: unless otherwise specified, ac disconnect specifications require the following conditions: the detect pin is connected to the port as shown in figure 1, a valid sine wave is applied to oscin, the oscfail bit is cleared and the ac disconnect enable bits are set. note 11: guaranteed by design, not subject to test. note 12: values measured at v ild and v ihd . note 13: if fault occurs during an i 2 c transaction, the int pin will not be pulled down until a stop condition is present on the i 2 c bus. note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: dgnd and agnd should be tied together in normal operation. note 3: an internal clamp limits the gate pins to a minimum of 12v above v ee . driving this pin beyond the clamp may damage the part. note 4: when a port powers on or off, the transient voltage on the port couples through c det (figure 16). the ltc4259a contains internal protection circuitry to withstand transient currents of up to 80ma for 5ms. as long as the absolute value of the current remains below 80ma, the ltc4259a will keep the voltage at the detect n pin within the absolute maximum voltage range. a properly sized r det should limit the current to less than 60ma. note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125 c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 6: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground (agnd and dgnd) unless otherwise specified.
ltc4259a 5 4259afb typical perfor a ce characteristics uw 50ms/div 4259 g01 gnd port voltage 10v/div v ee port 1 v dd = 3.3v v ee = C48v detection phase 1 classification power on detection phase 2 5ms/div 4259 g02 gnd port voltage 20v/div gate voltage 10v/div port current 500ma/div v ee v ee v ee +14v v dd = 3.3v v ee = C48v 0ma foldback 425ma current limit fet on load fully charged v sense n (mv) 225 200 175 150 125 100 75 50 25 0 450 400 350 300 250 200 150 100 50 0 v out n -agnd (v) C48 0 4259 g03 C40 C24 C32 C16 C8 i limit with r sense = 0.5 ? (ma) v dd = 3.3v v ee = C48v t a = 25 c load current (ma) 0 pull-down voltage (v) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 20 4259 g04 5 10 15 25 v dd = 3.3v t a = 25 c 50 s/div 4258 g05 port voltage 1v/div port current 20ma/div v dd = 3.3v v ee = C48v t a = 25 c 0ma C18v 40ma classification current (ma) 0 C2 C4 C6 C8 C10 C12 C14 C16 C18 C20 classification voltage (v) 4258 g06 0 10203040506070 detect n pin voltage port voltage with typical cmpd3003 v dd = 3.3v v ee = C48v t a = 25 c v ee supply voltage (v) C70 supply current (ma) 3.0 2.5 2.0 1.5 1.0 0.5 0 C40 C20 4258 g07 C60 C50 C30 C10 0 v dd = 3.3v reg 12h = 00h power on sequence in auto mode current limit foldback powering on a 180 f load int and sdaout pull down voltage vs load current classification transient response to 40ma load step classification current compliance v ee dc supply current vs supply voltage
ltc4259a 6 4259afb figure 3. current limit timing figure 4. dc disconnect timing figure 5. ac disconnect timing test ti i g w u figure 6. i 2 c interface timing figure 2. detect, class and turn-on timing in auto or semiauto modes scl sda t 1 t 2 t 3 t r t f t 5 t 6 t 7 t 8 t 4 4259a f06 0v v port n v gate n int pd inserted v ee v class v t port turn on (auto mode) t clsdly t class 4259a f02 t detdly t det t pon v lim v cut 0v v sense n to v ee int 4259a f03 t start , t icut v min v sense n to v ee int t dis t vmin 4259a f04 int i detect n v out n v oscin t dis i acdmin pd removed 4259a f05
ltc4259a 7 4259afb figure 9. reading the interrupt register (short form) figure 7. writing to a register figure 8. reading from a register figure 10. reading from alert response address ti i g diagra s w u w scl sda 4259a f07 00 1 ad3 ad2 ad1 ad0 a7 a6 a5 a4 a3 a2 a1 a0 r/w ack d7 d6 d5 d4 d3 d2 d1 d0 ack ack start by master ack by slave ack by slave ack by slave frame 1 serial bus address byte frame 2 register address byte frame 3 data byte stop by master scl sda 00 1 ad3 ad2 ad1 ad0 a7 a6 a5 a4 a3 a2 a1 a0 r/w ack ack 00 1 ad3 ad2 ad1 ad0 d7 d6 d5 d4 d3 d2 d1 d0 r/w ack ack start by master ack by slave ack by slave 4259a f08 stop by master repeated start by master ack by slave no ack by master frame 1 serial bus address byte frame 2 register address byte frame 1 serial bus address byte frame 2 data byte scl sda 4259a f09 01 0 ad3 ad2 ad1 ad0 d7 d6 d5 d4 d3 d2 d1 d0 r/w ack ack start by master ack by slave no ack by master frame 1 serial bus address byte frame 2 data byte stop by master scl sda 4259a f10 00 1 1 0 ad3 0 0 0 0 1 ad2 ad1 ad0 r/w ack ack 1 start by master ack by slave no ack by master frame 1 alert response address byte frame 2 serial bus address byte stop by master
ltc4259a 8 4259afb uu u pi fu ctio s reset (pin 1): chip reset, active low. when the reset pin is low, the ltc4259a is held inactive with all ports off and all internal registers reset to their power-up states. when reset is pulled high, the ltc4259a begins normal operation. reset can be connected to an external capaci- tor or rc network to provide a power turn-on delay. internal filtering of the reset pin prevents glitches less than 1 s wide from resetting the ltc4259a. pull reset high with 10k or tie to v dd . byp (pin 2): bypass output. the byp pin is used to connect the internally generated C 20v supply to an exter- nal 0.1 f bypass capacitor. use a 100v rated 0.1 f, x7r capacitor. do not connect the byp pin to any other external circuitry. int (pin 3): interrupt output, open drain. int will pull low when any one of several events occur in the ltc4259a. it will return to a high impedance state when bits 6 or 7 are set in the reset pb register (1ah). the int signal can be used to generate an interrupt to the host processor, eliminating the need for continuous software polling. individual int events can be disabled using the int mask register (01h). see register functions and applications information for more information. the int pin is only updated between i 2 c transactions. scl (pin 4): serial clock input. high impedance clock input for the i 2 c serial interface bus. the scl pin should be connected directly to the i 2 c scl bus line. sdaout (pin 5): serial data output, open drain data output for the i 2 c serial interface bus. the ltc4259a uses two pins to implement the bidirectional sda function to simplify optoisolation of the i 2 c bus. to implement a stan- dard bidirectional sda pin, tie sdaout and sdain together. see applications information for more information. sdain (pin 6): serial data input. high impedance data input for the i 2 c serial interface bus. the ltc4259a uses two pins to implement the bidirectional sda function to sim- plify optoisolation of the i 2 c bus. to implement a standard bidirectional sda pin, tie sdaout and sdain together. see applications information for more information. ad3 (pin 7): address bit 3. tie the address pins high or low to set the i 2 c serial address to which the ltc4259a responds. this address will be (010a 3 a 2 a 1 a 0 ) b . pull ad3 high or low with 10k or tie to v dd or dgnd. ad2 (pin 8): address bit 2. see ad3. ad1 (pin 9): address bit 1. see ad3. ad0 (pin 10): address bit 0. see ad3. detect1 (pin 11): detect sense, port 1. the ltc4259a powered device (pd) detection, classification and ac disconnect hardware monitors port 1 with this pin. con- nect detect1 to the output port via a 0.47 f 100v x7r capacitor in series with a 1k resistor, both in parallel with a low leakage diode (see figure 1). the resistor and capacitor may be eliminated if ac disconnect is not used. if the port is unused, the detect1 pin can be tied to dgnd or allowed to float. detect2 (pin 12): detection sense, port 2. see detect1. detect3 (pin 13): detection sense, port 3. see detect1. detect4 (pin 14): detection sense, port 4. see detect1. dgnd (pin 15): digital ground. dgnd should be con- nected to the return from the 3.3v supply. dgnd and agnd should be tied together. v dd (pin 16): logic power supply. connect to a 3.3v power supply relative to dgnd. v dd must be bypassed to dgnd near the ltc4259a with at least a 0.1 f capacitor. shdn1 (pin 17): shutdown port 1, active low. when pulled low, shdn1 shuts down port 1, regardless of the state of the internal registers. pulling shdn1 low is equivalent to setting the reset port 1 bit in the reset pushbutton register (1ah). internal filtering of the shdn1 pin prevents glitches less than 1 s wide from reseting the ltc4259a. pull shdn1 high with 10k or tie to v dd . shdn2 (pin 18): shutdown port 2, active low. see shdn1. shdn3 (pin 19): shutdown port 3, active low. see shdn1. shdn4 (pin 20): shutdown port 4, active low. see shdn1.
ltc4259a 9 4259afb uu u pi fu ctio s agnd (pin 21): analog ground. agnd should be con- nected to the return from the C 48v supply. agnd and dgnd should be tied together. sense4 (pin 22): port 4 current sense input. sense4 monitors the external mosfet current via a 0.5 ? sense resistor between sense4 and v ee . whenever the voltage across the sense resistor exceeds the overcurrent detec- tion threshold v cut , the current limit fault timer counts up. if the voltage across the sense resistor reaches the current limit threshold v lim (typically 25mv/50ma higher), the gate4 pin voltage is lowered to maintain constant current in the external mosfet. see applications information for further details. if the port is unused, the sense4 pin must be tied to v ee . gate4 (pin 23): port 4 gate drive. gate4 should be connected to the gate of the external mosfet for port 4. when the mosfet is turned on, a 50 a pull-up current source is connected to the pin. the gate voltage is clamped to 13v (typ) above v ee . during a current limit condition, the voltage at gate4 will be reduced to maintain constant current through the external mosfet. if the fault timer expires, gate4 is pulled down with 50 a, turning the mosfet off and recording a t icut or t start event. if the port is unused, float the gate4 pin or tie it to v ee . out4 (pin 24): port 4 output voltage monitor. out4 should be connected to the output port through a 10k series resistor. a current limit foldback circuit limits the power dissipation in the external mosfet by reducing the current limit threshold when the port voltage is within 18v of agnd. the port 4 power good bit is set when the voltage from out4 to v ee drops below 2v (typ). a 2.5m ? resistor is connected internally from out4 to agnd. if the port is unused, the out4 pin can be tied to agnd or allowed to float. sense3 (pin 25): port 3 current sense input. see sense4. gate3 (pin 26): port 3 gate drive. see gate4. out3 (pin 27): port 3 output voltage monitor. see out4. v ee (pin 28): C 48v supply input. connect to a C 48v to C 57v supply, relative to agnd. sense2 (pin 29): port 2 current sense input. see sense4. gate2 (pin 30): port 2 gate drive. see gate4. out2 (pin 31): port 2 output voltage monitor. see out4. sense1 (pin 32): port 1 current sense input. see sense4. gate1 (pin 33): port 1 gate drive. see gate 4. out1 (pin 34): port 1 output voltage monitor. see out4. auto (pin 35): auto mode input. auto mode allows the ltc4259a to detect and power up a pd even if there is no host controller present on the i 2 c bus. the voltage of the auto pin determines the state of the internal registers when the ltc4259a is reset or comes out of v dd uvlo (see the register map in table 1). the states of these register bits can subsequently be changed via the i 2 c interface. the real-time state of the auto pin is read at bit 0 in the pin status register (11h). pull auto high or low with 10k or tie to v dd or dgnd. oscin (pin 36): oscillator input. connect to an oscillating signal source, preferably a sine wave, of approximately 100hz with 2v peak-to-peak amplitude, negative peaks above C 0.3v and positive peaks below 2.5v. when a port is powered and ac disconnect is enabled, this signal is amplified and driven onto the appropriate detect pin to determine the ac impedance of the pd.
ltc4259a 10 4259afb * the start-up state of the v ee uvlo and osc fail bits depend on the order in which the v dd and v ee supplies are brought up. the v dd uvlo bit is not set by the reset pin or the reset all push button. encoding class status detect status mode bit encoding 000 class status unknown 000 detect status unknown 00 shutdown power off, detection and class off 001 class 1 001 short circuit (<1v) 01 manual will not advance between states 010 class 2 010 reserved 10 semiauto detect and class but wait to turn on power 011 class 3 011 rlow 11 auto detect, class and power automatically 100 class 4 100 detect good 101 undefinedread as class 0 101 rhigh 110 class 0 110 open circuit 111 overcurrent 111 reserved key: ro = read only r/w = read/write cor = clear on read wo = write only address register name r/w port bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state reset state interrupts auto pin low auto pin high 00h interrupt ro global supply event t start fault t icut fault class complete detect complete disconnect pwr good event pwr enable event 1000,0000 1000,0000 01h int mask r/w global mask 7 mask 6 mask 5 mask 4 mask 3 mask 2 mask 1 mask 0 1000,0000 1110,0100 events 02h power event ro 4321 pwr good pwr good pwr good pwr good pwr enable pwr enable pwr enable pwr enable 0000,0000 0000,0000 03h power event cor cor change 4 change 3 change 2 change 1 change 4 change 3 change 2 change 1 04h detect event ro 4321 class complete 4 class complete 3 class complete 2 class complete 1 detect complete 4 detect complete 3 detect c omplete 2 detect complete 1 0000,0000 0000,0000 05h detect event cor cor 06h fault event ro 4321 disconnect 4 disconnect 3 disconnect 2 disconnect 1 t icut fault 4 t icut fault 3 t icut fault 2 t icut fault 1 0000,0000 0000,0000 07h fault event cor cor 08h t start event ro 4321 reserved reserved reserved reserved t start fault 4 t start fault 3 t start fault 2 t start fault 1 0000,0000 0000,0000 09h t start event cor cor 0ah supply event ro global over temp reserved v dd uvlo v ee uvlo reserved reserved osc fail reserved 0011,0010* 0011,0010* 0bh supply event cor cor status 0ch port 1 status ro 1 reserved class status 2 class status 1 class status 0 reserved detect status 2 detect status 1 detect status 0 0000, 0000 0000,0000 0dh port 2 status ro 2 reserved class status 2 class status 1 class status 0 reserved detect status 2 detect status 1 detect status 0 0000, 0000 0000,0000 0eh port 3 status ro 3 reserved class status 2 class status 1 class status 0 reserved detect status 2 detect status 1 detect status 0 0000, 0000 0000,0000 0fh port 4 status ro 4 reserved class status 2 class status 1 class status 0 reserved detect status 2 detect status 1 detect status 0 0000, 0000 0000,0000 10h power status ro 4321 power good 4 power good 3 power good 2 power good 1 power enable 4 power enable 3 power enable 2 power enable 1 00 00,0000 0000,0000 11h pin status ro global reserved reserved ad3 pin status ad2 pin status ad1 pin status ad0 pin status reserved auto pin status 00a 3 a 2 ,a 1 a 0 00 00a 3 a 2 ,a 1 a 0 01 configuration 12h operating mode r/w 4321 port 4 mode 1 port 4 mode 0 port 3 mode 1 port 3 mode 0 port 2 mode 1 port 2 mode 0 port 1 mode 1 port 1 mode 0 0000,0000 1111,1111 13h disconnect enable r/w 4321 ac discon en 4 ac discon en 3 ac discon en 2 ac discon en 1 dc discon en 4 dc discon en 3 dc discon en 2 dc discon en 1 0000,0000 1111,0000 14h detect/class enable r/w 4321 class enable 4 class enable 3 class enable 2 class enable 1 detect enable 4 detect enable 3 detect enable 2 detect enable 1 0000 ,0000 1111,1111 15h reserved r/w reserved reserved reserved reserved reserved reserved reserved reserved 0000,0000 0000,0000 16h timing config r/w global reserved reserved t start1 t start0 t icut1 t icut0 t dis1 t dis0 0000,0000 0000,0000 17h misc config r/w global interrupt pin reserved osc fail reserved reserved reserved reserved reserved 1010,0000 1010,0000 enable mask pushbuttons 18h det/class restart pb wo 4321 restart class 4 restart class 3 restart class 2 restart class 1 restart detect 4 restart detect 3 restart detect 2 restart detec t 1 0000,0000 0000,0000 19h power enable pb wo 4321 power off 4 power off 3 power off 2 power off 1 power on 4 power on 3 power on 2 power on 1 0000,0000 0000,0000 1ah reset pb wo global clear all clear interrupt pin reserved reset all reset port 4 reset port 3 reset port 2 reset port 1 0000,0000 0000,0 000 interrupts table 1. register ap w
ltc4259a 11 4259afb interrupt registers interrupt (address 00h): interrupt register, read only. a transition to logical 1 of any bit in this register will assert the int pin (pin 3) if the corresponding bit in the int mask register is set. each bit is the logical or of the correspond- ing bits in the event registers. the interrupt register is read only and its bits cannot be cleared directly. to clear a bit in the interrupt register, clear the corresponding bits in the appropriate status or event registers or set bit 7 in the reset pushbutton register (1ah). int mask (address 01h): interrupt mask, read/write. a logic 1 in any bit of the int mask register allows the correspond- ing interrupt register bit to assert the int pin if it is set. a logic 0 in any bit of the int mask register prevents the cor- responding interrupt bit from affecting the int pin. the actual interrupt register bits are unaffected by the state of the int mask register. event registers power event (address 02h): power event register, read only. the lower four bits in this register indicate that the corresponding port power enable status bit has changed; the logical or of these four bits appears in the interrupt register as the pwr enable event bit. the upper four bits indicate that the corresponding port power good status bit has changed; the logical or of these four bits appears in the interrupt register as the pwr good event bit. the power event bits latch high and will remain high until cleared by reading from address 03h. power event cor (address 03h): power event register, clear on read. read this address to clear the power event register. address 03h returns the same data as address 02h and reading address 03h clears all bits at both addresses. detect event (address 04h): detect event register, read only. the lower four bits in this register indicate that at least one detection cycle for the corresponding port has com- pleted; the logical or of these four bits appears in the in- terrupt register as the detect complete bit. the upper four bits indicate that at least one classification cycle for the corresponding port has completed; the logical or of these four bits appears in the interrupt register as the class com- plete bit. in manual mode, this register indicates that the requested detection/classification cycle has completed and register fu ctio s u u the ltc4259a is awaiting further instructions. in semiauto or auto modes, these bits indicate that the detect status and class status bits in the port status registers are valid. the detect event bits latch high and will remain high until cleared by reading from address 05h. detect event cor (address 05h): detect event register, clear on read. read this address to clear the detect event register. address 05h returns the same data as address 04h, and reading address 05h clears all bits at both addresses. fault event (address 06h): fault event register, read only. the lower four bits in this register indicate that a t icut fault has occurred at the corresponding port; the logi- cal or of these four bits appears in the interrupt register as the t icut fault bit. the upper four bits indicate that a dis- connect event has occurred at the corresponding port; the logical or of these four bits appears in the interrupt reg- ister as the disconnect bit. the fault event bits latch high and will remain high until cleared by reading from address 07h. fault event cor (address 07h): fault event register, clear on read. read this address to clear the fault event regis- ter. address 07h returns the same data as address 06h and reading address 07h clears all bits at both addresses. t start event (address 08h): t start event register, read only. the lower four bits in this register indicate that a t start fault has occurred at the corresponding port; the logical or of these four bits appears in the interrupt register as the t start fault bit. the t start event bits latch high and will remain high until cleared by reading from address 09h. the upper four bits in this register are reserved and will always read as 0. t start event cor (address 09h): t start event register, clear on read. read this address to clear the fault event register. address 09h returns the same data as address 08h and reading address 09h clears all bits at both addresses. supply event (address 0ah): supply event register, read only. bit 1, osc fail, sets when the signal at pin 36, oscin, is absent or does not have the required amplitude and ac disconnect cannot operate properly. the osc fail bit latches high and will remain high until cleared by reading at 0bh. the osc fail bit is set after power on or reset unless the v ee supply is not present. power is removed on ports with ac
ltc4259a 12 4259afb disconnect enabled independently of the state of the osc fail bit. see ac disconnect under applications information for more details. bit 4 indicates that v ee has dropped be- low the v ee uvlo level (typically C28v). bit 5 signals that the v dd supply has dropped below the v dd uvlo thresh- old. bit 7 indicates that the ltc4259a die temperature has exceeded its thermal shutdown limit (see note 5 under electrical characteristics). the logical or of bits 1, 4, 5 and 7 appears in the interrupt register as the supply fault bit. see the misc config register for information on masking the osc fail bit out of the supply fault interrupt. the remaining bits in the register are reserved and will always read as 0. the supply event bits latch high and will remain high until cleared by reading from address 0bh. supply event cor (address 0bh): supply event register, clear on read. read this address to clear the fault event register. address 0bh returns the same data as address 0ah, and reading address 0bh clears all bits at both addresses. status registers port 1 status (address 0ch): port 1 status register, read only. this register reports the most recent detection and classification results for port 1. bits 0-2 report the status of the most recent detection attempt at the port and bits 4-6 report the status of the most recent classification attempt at the port. if power is on, these bits report the detection/ classification status present just before power was turned on. if power is turned off at the port for any reason, all bits in this register will be cleared. see table 1 for detection and classification status bit encoding. port 2 status (address 0dh): port 2 status register, read only. see port 1 status. port 3 status (address 0eh): port 3 status register, read only. see port 1 status. port 4 status (address 0fh): port 4 status register, read only. see port 1 status. power status (address 10h): power status register, read only. the lower four bits in this register report the switch on/off state for the corresponding ports. the upper four bits (the power good bits) indicate that the drop across the power switch and sense resistor for the corresponding ports is less than 2v (typ) and power start-up is complete. the power good bits are latched high and are only cleared when a port is turned off or the ltc4259a is reset. pin status (address 11h): external pin status, read only. this register reports the real time status of the auto (pin 35) and ad0-ad3 (pins 7-10) digital input pins. the logic state of the auto pin appears at bit 0 and the ad0-ad3 pins at bits 2-5. the remaining bits are reserved and will read as 0. auto affects the initial states of some of the ltc4259a configuration registers at start-up but has no effect after start-up and can be used as a general purpose input if desired, as long as it is guaranteed to be in the appropriate state at start-up. configuration registers operating mode (address 12h): operating mode configu- ration, read/write. this register contains the mode bits for each of the four ports in the ltc4259a. see table 1 for mode bit encoding. at power-up, all bits in this register will be set to the logic state of the auto pin (pin 35). see operating modes in the applications information section. disconnect enable (address 13h): disconnect enable register, read/write. the lower four bits of this register enable or disable dc disconnect detection circuitry at the corresponding port. if the dc discon enable bit is set the port circuitry will turn off power if the current draw at the port falls below i min for more than t dis . i min is equal to v min / r s , where r s is the sense resistor and should be 0.5 ? for ieee 802.3af compliance. if the bit is clear the port will not remove power due to low current. the upper four bits enable or disable ac disconnect on the corresponding port. when a ports ac disconnect bit is set, the ltc4259a senses the impedance of that port by forc- ing an ac voltage on the ports detect pin and measuring the ac current. if the detect pin sinks less than i acdmin for more than t dis , the port will turn off power. if the bit is clear, the port will not remove power due to high port impedance (ac current below i acdmin ). the dc and ac disconnect signals that reset t dis are ored together and either sensing method (if they are both en- abled) will keep the port powered. a port with neither dc or ac disconnect enabled will not power off automatically when the pd is removed. register fu ctio s u u
ltc4259a 13 4259afb involves reading the register to determine its status, set- ting the appropriate bit in software and writing back the entire register, a pushbutton register allows a single bit to be written without knowing or affecting the status of the other bits in the register. pushbutton registers are write- only and will return 00h if read. det/class restart pb (address 18h): detection/classifi- cation restart pushbutton register, write only. writing a 1 to any bit in this register will start or restart a single detection or classification cycle at the corresponding port in manual mode. it can also be used to set the correspond- ing bits in the detect/class enable register (address 14h) for ports in auto or semiauto mode. the lower 4 bits affect detection on each port while the upper 4 bits affect classification. power enable pb (address 19h): power enable pushbutton register, write only. the lower four bits of this register set the power enable bit in the corresponding port status reg- ister; the upper four bits clear the corresponding power enable bit. setting or clearing the power enable bits via this register will turn on or off the power in any mode except shutdown, regardless of the state of detection or classifi- cation. note that t icut , t start and disconnect events (if enabled) will still turn off power if they occur. the power enable bit cannot be set if the port has turned off due to a t icut or t start fault and the t icut timer has not yet counted back to zero. see applications information for more information on t icut timing. clearing the power enable bits with this register also clears the detect and fault event bits, the port status register, and the detection and classification enable bits for the affected port(s). reset pb (address 1ah): reset pushbutton, write only. bits 0-3 reset the corresponding port by clearing the power enable bit, the detect and fault event bits, the status regis- ter and the detection and classification enable bits for that port. bit 4 returns the entire ltc4259a to the power-on reset state; all ports are turned off, the auto pin is reread and all registers are returned to their power-on defaults, except v dd uvlo, which remains cleared. bit 5 is reserved; setting it has no effect. setting bit 6 releases the interrupt pin if it is asserted without affecting the event registers or the interrupt register. when the int pin is released in this detect/class enable (address 14h): detection and clas- sification enable, read/write. the lower four bits of this reg- ister enable the detection circuitry at the corresponding port if that port is in auto or semiauto mode. the upper four bits enable the classification circuitry at the corresponding port if that port is in auto or semiauto mode. in manual mode, setting a bit in this register will cause the ltc4259a to per- form one classification or detection cycle on the corre- sponding port. writing to the detect/class restart pb (18h) has the same effect without disturbing the detect/class enable bits for other ports. timing config (address 16h): global timing configuration, read/write. bits 0-1 program t dis , the time duration before a port is automatically tuned off after the pd is removed. the ltc4259a can be programmed to monitor whether port current is below i min (dc connect) or port impedance is high (ac disconnect). bits 2-3 program t icut , the time during which a ports current can exceed i cut without it being turned off. if the current is still above i cut after t icut , the ltc4259a will indicate a t icut fault and turn the port off. bits 4-5 program t start , the time duration before an over- current condition during port power-on is considered a t start fault and the port is turned off. note that using the t icut and t start times other than the default is not compli- ant with ieee 802.3af and may double or quadruple the energy dissipated by the external mosfets during fault con- ditions. bits 6-7 are reserved and should be read/written as 0. see electrical characteristics for timer bit encoding. also see the applications information for descriptions of t start , t icut , dc and ac disconnect timing. misc config (address 17h): miscellaneous configuration, read/write. bit 5 is the osc fail mask; it is set by default. when the osc fail mask bit is clear, it prevents a failure on the oscin pin from setting the osc fail bit and causing a supply event interrupt. setting bit 7 enables the int pin. if this bit is reset, the ltc4259a will not pull down the int pin in any condition nor will it respond to the alert response address. this bit is set by default. pushbutton registers note regarding pushbutton registers: pushbutton reg- isters are specialized registers that trigger an event when a 1 is written to a bit; writing a 0 to a bit will do nothing. unlike a standard read/write register, where setting a single bit register fu ctio s u u
ltc4259a 14 4259afb applicatio s i for atio wu uu figure 11. power over ethernet system diagram overview over the years, twisted-pair ethernet has become the most commonly used method for local area networking. the ieee 802.3 group, the originator of the ethernet standard, has defined an extension to the standard, known as 802.3af, which allows dc power to be delivered simulta- neously over the same cable used for data communica- tion. this promises a whole new class of ethernet devices, including ip telephones, wireless access points, and pda charging stations, which do not require additional ac wiring or external power transformers, a.k.a. wall warts. with about 13w of power available, small data devices can be powered by their ethernet connections, free from ac wall outlets. sophisticated detection and power monitor- ing techniques prevent damage to legacy data-only de- vices, while still supplying power to newer, ethernet- powered devices over the twisted-pair cable. a device that supplies power is called power sourcing equipment (pse); a device that draws power from the wire is called a powered device (pd). a pse is typically an ethernet switch, router, hub, or other network switching equipment that is commonly found in the wiring closets where cables converge. pds can take many forms: digital ip telephones, wireless network access points, pda or notebook computer docking stations, cell phone charg- ers, and hvac thermostats are examples of devices that can draw power from the network. a pse is required to provide a nominal 48v dc between either the signal pairs or the spare pairs (but not both) as shown in figure 11. the power is applied as a voltage between two of the pairs, typically by powering the center- taps of the isolation transformers used to couple the differential data signals to the wire. since ethernet data is transformer coupled at both ends and is sent differentially, a voltage difference between the transmit pairs and the receive pairs does not affect the data. a 10base-t/ 100base-tx ethernet connection only uses 2 of the 4 pairs in the cable. the unused or spare pairs can be powered directly, as shown in figure 11, without affecting the data. however, 1000base-t uses all 4 pairs and power must be connected to the transformer center taps if compatibility with 1000base-t is required. register fu ctio s u u way, the condition causing the ltc4259a to pull the int pin down must be removed before the ltc4259a will be able to pull int down again. this can be done by reading and clearing the event registers or by writing a 1 into bit 7 of this register. setting bit 7 releases the interrupt pin, clears all the event registers and clears all the bits in the interrupt register. 4259a f11 smaj58a 58v 0.1 f tx rx rx tx smaj58a 58v data pair data pair v ee sense gate out v dd int scl sdain sdaout cmpd3003 10k 1k 0.1 f 100v 0.5 ? irfm120a s1b spare pair spare pair 1/4 ltc4259a dgnd byp agnd detect i 2 c 3.3v interrupt C48v cat 5 20 ? max roundtrip 0.05 f max rj45 4 5 4 5 1 2 1 2 3 6 3 6 7 8 7 8 rj45 1n4002 4 1n4002 4 pse pd r class C48v in pwrgd C48v out ltc4257 gnd dc/dc converter 5 f c in 300 f + C v out gnd 0.47 f 100v x7r 0.1 f
ltc4259a 15 4259afb applicatio s i for atio wu uu the ltc4259a provides a complete solution for detection and powering of pd devices in an ieee 802.3af compliant system. the ltc4259a consists of four independent ports, each with the ability to detect, classify, and provide isolated C48v power to a pd device connected to it. the ltc4259a senses removal of a pd with ieee 802.3af compliant ac or dc methods and turns off C48v power when the pd is removed. an internal control circuit takes care of system configuration and timing, and uses an i 2 c interface to communicate with the host system. operating modes each ltc4259a port can operate in one of four modes: manual, semiauto, auto or shutdown. the operating mode for a port is set by the appropriate bits in the operating mode register. the ltc4259a will power up with all ports in shutdown mode if the external auto pin is tied low; if auto is high, all ports will wake up in auto mode. the operating mode can be changed at any time via the i 2 c interface, regardless of the state of the auto pin. ? in manual mode, a port will wait for instructions from the host system before taking any action. it will run single detection or classification cycles when com- manded, and will report results in the port status registers. when the host system decides it is time to turn on or off power to a port, it can do so by setting the appropriate power on/off bits in the power enable pb register regardless of the current status of detec- tion or classification. ? in semiauto mode, the port will repeatedly attempt to detect and classify a pd device attached to the link. it will report this information in its port status register, and wait for the host system to set the appropriate power on bit in the power enable pb register before applying power to the port. ? in auto mode, the port will detect and classify a pd device connected to it, then immediately turn on the power if detection was successful regardless of the result of classification. ? in shutdown mode, the port is disabled and will not detect or power a pd. also, the detect and fault event bits, status bits and enable bits for the port are reset to zero. regardless of which mode it is in, the ltc4259a will remove power automatically from any port that generates a t start or t icut overcurrent fault event (see t icut timing and t start timing sections). it will also automatically remove power from any port that generates a disconnect event if the appropriate disconnect enable bit is set in the disconnect enable register. the host controller may also remove power at any time by setting the appropriate power off bit in the power enable pb register. power-on reset at turn-on or any time the ltc4259a is reset (either by pulling the reset pin low or writing to the global reset all bit), all the ports turn off and all internal registers go to a predefined state, shown in table 1. several of the registers assume different states based on the state of the auto pin at reset. the default states with auto high allow the ltc4259a to detect and power up a pd in automatic mode, even if nothing is connected to the i 2 c interface. signature detection the ieee defines a specific pair-to-pair pd signature resistance that identifies a device that can accept power over ethernet in accordance with the 802.3af specifica- tion. when the port voltage is below 10v, an 802.3af compliant pd will have a 25k signature resistance. figure 12 illustrates the relationship between the pd signature resistance (white box from 23.75k to 26.25k) and required resistance ranges the pse must accept (white box) and reject (gray boxes). according to the 802.3af specifica- tion, the pse may or may not accept resistances in the two ranges of 15k to 19k and 26.5k to 33k. note that the black box in figure 12 represents the 150 ? pair-to-pair termina- tion used in legacy 802.3 devices like a computers net- work interface card (nic) that cannot accept power. figure 12. ieee 802.3af signature resistance ranges resistance pd pse 0 ? 10k 15k 4259a f12 19k 26.5k 26.25k 23.75k 150 ? (nic) 20k 30k 33k
ltc4259a 16 4259afb the ltc4259a checks for the signature resistance by forcing two test currents on the port (via the detect n pins) in sequence and measuring the resulting voltages. it then subtracts the two v-i points to determine the resistive slope while removing voltage offset caused by any series diodes or current offset caused by leakage at the port (see figure 13). the ltc4259a will typically accept any pd resistance between 17k and 29k as a valid pd and report detect good (100 binary) in the detect status bits (bits 2 through 0) of the corresponding port status register. values outside this range, including open and short cir- cuits, are also reported in the detect status bits. refer to table 1 for a complete decoding of the detect status bits. the first test point is taken by forcing a test current into the port, waiting a short time to allow the line to settle and measuring the resulting voltage. this result is stored and the second current is applied to the port, allowed to settle and the voltage measured. each point takes 100ms to measure, and an entire detection cycle takes 200ms. the ltc4259a will not report detect good if the pd has more than 5 f in parallel with its signature resistor. the ports operating mode controls if and when the ltc4259a runs a detection cycle. in manual mode, the port will sit idle until a restart detection (register 18h) command is received. it will then run a complete 200ms detection cycle on the selected port, report the results in the detect status bits in the corresponding port status register and return to idle until another command is received. in semiauto mode, the ltc4259a autonomously tests valid pds connected to the ports but it will not apply power until instructed to do so by the host controller. it repeatedly queries the port every 320ms and updates the detect status bits at the end of each cycle. if a detect good is reported, it will advance to the classification phase and report that result in the port status register. until in- structed to do otherwise, the ltc4259a will continue to repeat detection on the port. behavior in auto mode is similar to semiauto; however, after a detect good is reported, the ltc4259a performs the classification phase and then powers up the port without further intervention. the signature detection circuitry is disabled when the port is in shutdown mode, powered up or the corresponding detect enable bit is cleared. classification a pd has the option of presenting a classification signa- ture to the pse to indicate how much power it will draw when powered up. this signature consists of a specific constant current draw when the pse port voltage is between 15.5v and 20.5v, with the current level indicating the power class to which the pd belongs. per the ieee 802.3af speci- fication, the ltc4259a identifies the five classes of pd listed in table 2. during classification, the ltc4259a controls and applicatio s i for atio wu uu figure 13. pd detection table 2. ieee 802.3af powered device classes ieee 802.3af classification maximum minimum pse class current at pse pd power output power class description 0 0ma to 5ma 12.95w 15.4w pd does not implement classification, unknown power 1 8ma to 13ma 3.84w 4w low power pd 2 16ma to 21ma 6.49w 7w medium power pd 3 25ma to 31ma 12.95w 15.4w high or full power pd 4 35ma to 45ma 12.95w 15.4w reserved, power as class o first detection point second detection point valid pd 25k ? slope 275 165 current ( a) 0v-2v offset voltage 4259a f13
ltc4259a 17 4259afb measures the port voltage through the detect n pin. note that class 4 is presently specified by the ieee as reserved for future use. figure 14 shows a pd load line, starting with the shallow slope of the 25k signature resistor below 10v, then drawing the classification current (in this case, class 3) between 14.5v and 20.5v. the ltc4259as load line for classification is also shown in figure 14. it has low imped- ance until current limit at 65ma (typ). the ltc4259a will classify a port immediately after a successful detection cycle in semiauto or auto modes, or when commanded to in manual mode. it measures the pd classification signature current by applying 18v (typ) to the port and measuring the resulting current. it reports the detected class in the class status bits in the correspond- ing port status register. note that in auto mode, the port will power up regardless of which class is detected. the classification circuitry is disabled when the port is in shutdown mode, powered up, or the corresponding class enable bit is cleared. gate currents once the decision has been made to turn on power to a port, the ltc4259a uses a 50 a current source to pull up on the gate pin. under normal power-up circumstances, the mosfet gate will charge up rapidly to v t (the mosfet threshold voltage), the mosfet current will rise quickly to the current limit level and the gate pin will be servoed to maintain the proper i inrush charging current. when out- put charging is complete, the mosfet current will fall and the gate pin will be allowed to continue rising to fully enhance the mosfet and minimize its on resistance. the final v gs is nominally 13v. when a port is turned off, a 50 a current source pulls down on the gate pin, turning the mosfet off in a controlled manner. no external capacitors no external capacitors are required on the gate pins for active current limit stability, lowering part count and cost. this also allows the fastest possible turn-off under severe overcurrent conditions, providing maximum safety and protection for the mosfets, load devices and board traces. connecting capacitors to the external mosfet gates can adversely affect the ltc4259as ability to respond to a shorted port. inrush control the 802.3af standard lists two separate maximum current limits, i lim and i inrush . because they have identical val- ues, the ltc4259a implements both as a single current limit using v lim (described below). their functions are differentiated through the use of t icut and t start , respec- tively (see t icut timing and t start timing sections). to maintain consistency with the standard, the i inrush term is used when referring to an initial t start power-up event. when the ltc4259a turns on a port, it turns on the mosfet by pulling up on the gate. the ltc4259a is designed to power up the port in current limit, limiting the inrush current to i inrush . the port voltage will quickly rise to the point where the pd reaches its input turn-on threshold and begins to draw current to charge its bypass capacitance, slowing the rate of port voltage increase. applicatio s i for atio wu uu figure 14. pd classification voltage (v class ) 0 current (ma) 60 50 40 30 20 10 0 5101520 4259a f14 25 typical class 3 pd load line 48ma 33ma pse load line 23ma 14.5ma 6.5ma class 4 class 2 class 1 class 0 class 3 over current power control the primary function of the ltc4259a is to control the delivery of power to the pse port. it does this by control- ling the gate drive voltage of an external power mosfet while monitoring the current via a sense resistor and the output voltage at the out pin. this circuitry serves to couple the raw isolated C48v input supply to the port in a controlled manner that satisfies the pds power needs while minimizing disturbances on the C48v backplane.
ltc4259a 18 4259afb dual-level current limit a pd is permitted to draw up to 15.4w continuously and up to 400ma for 50ms. the ltc4259a has two correspond- ing current limit thresholds, i cut (375ma typ) and i lim (425ma typ). these are given by the equations: i cut = v cut /r s , i lim = v lim /r s r s is the sense resistor and should be 0.5 ? for ieee 802.3af compliance. while the ltc4259a allows the port current to exceed i cut for a limited time period (see t icut timing below), it does not allow the current to exceed i lim . the current limit circuit monitors the port current by monitoring the voltage across the sense resistor and re- duces the mosfet gate voltage as needed to keep the current at or below i lim . when the current drops below i lim , the gate voltage is restored to the full value to keep the mosfet resistance to a minimum. t icut timing whenever more than i cut = v cut /r s flows through a port, the ports sense voltage is above v cut and the t icut timer counts up. the t icut timer also counts up when the ports out pin voltage is above v pg . if either of these conditions persists and the t icut timer expires, the ltc4259a will turn off power to the port immediately and set the appropriate t icut fault bit in register 06h/07h. the t icut duration can be programmed via register 16h, bits 2 and 3 (table 1). the t icut timer is an up/down counter that is designed to protect the external mosfet from thermal stress caused by repeatedly operating in current limit. the counter counts up whenever the current is above i cut and counts down at 1/16th the rate when it is not. the counter will bottom out at zero to prevent underflow. full count indi- cates that the t icut timer has expired and the port will be turned off. this count up/count down behavior implements duty cycle protection, preventing intermittent current limit faults from causing cumulative thermal stress in the mosfet. if the port enters current limit but then exits before the timer expires, the count will decrease slowly, giving the i cut timer the ability to turn off sooner in the case of a repetitive fault. if the overcurrent duty cycle is less than 6.3% the t icut timer will be fully reset. if the t icut timer expires and causes the port to shut off, the timer will continue to run, counting down at the slow 1/16th rate and preventing the port from being repowered until the count returns to zero. this protects the mosfet from damage due to a faulty pd that may still have a valid signature, or from errant software that repeatedly writes to the power on bit. the port will not repower until after the t icut counter returns to zero. in manual and semiauto modes the power enable command must be received after the t icut counter reaches zero. in auto mode the ltc4259a must complete a valid detection cycle after the t icut counter reaches zero. t start timing to distinguish between normal turn-on current limit be- havior and current limit faults which occur after power-up is complete, the ltc4259a starts a timer (the t start timer) whenever a power-up sequence begins. the t start timer serves three functions. first and fore- most, it allows the user to specify a different current limit timeout (t start instead of t icut ) during turn-on (current limit duty cycle protection remains functional). second, the dc disconnect timer is disabled during this period and can only begin counting up after the t start timer has expired. together, these two features let the pd draw the maximum current i inrush to charge its input capacitance, boot up and begin drawing power without triggering a t start fault. finally, if the device is in current limit for the entire t start period, a t start fault will be generated instead of a t icut fault. this can be useful for tracking down the cause of an overcurrent fault. as long as the pd draws less than i cut at the end of t start and begins drawing the minimum current within t dis after t start expires (if dc disconnect is enabled), no faults will be indicated. the t start timer also implements the duty cycle protec- tion described under t icut timing and its duration can be programmed via register 16h, bits 5 and 4 (table 1). applicatio s i for atio wu uu
ltc4259a 19 4259afb applicatio s i for atio wu uu foldback foldback is designed to limit power dissipation in the mosfet during power-up and momentary short-circuit conditions. at low port output voltages, the voltage across the mosfet is high, and power dissipation will be large if significant current is flowing. foldback monitors the port output voltage and reduces the v lim current limit level linearly from its full value (212.5mv typ) at a port voltage of 18v to approximately 1/7th of the full value (30mv typ) at a port voltage of 0v. with 0.5 ? sense resistors, this limits the short-circuit current to 60ma (typ) instead of the full 425ma (typ) current limit. when the ltc4259a is in foldback, the t icut timer is active. short-circuit protection if a port is suddenly shorted out, the mosfet power dissipation can rise to very high levels, jeopardizing the mosfet even before the normal current limit circuit can respond. a separate short-circuit current limit circuit watches for significant overcurrent events (v sense >275mv, >550ma with a 0.5 ? sense resistor) and pulls the gate pin down immediately if such an event occurs, shutting off the mosfet in less than 1 s (with no external capacitor on gate). approximately 100 s later, gate is allowed to rise back up and the normal current limit circuit will take over, allowing i lim current to flow and causing the t icut timer to count up. during a short circuit, i lim will be reduced by the foldback feature to 1/7th of the nominal value. choosing external mosfets power delivery to the ports is regulated with external power mosfets. these mosfets are controlled as previ- ously described to meet the ieee 802.3af specification. under normal operation, once the port is powered and the pds bypass capacitor is charged to the port voltage, the external mosfet dissipates very little power. this sug- gests that a small mosfet is adequate for the job. unfor- tunately, other requirements of the ieee 802.3af mandate a mosfet capable of dissipating significant power. when the port is being powered up, the port voltage must reach 30v or more before the pd turns on. the port voltage can then drop to 0v as the pds bypass capacitor is charged. according to the ieee, the pd can directly connect a 180 f capacitor to the port and the pse must charge that capacitor with a current limit of 400ma to 450ma for at least 50ms. an even more extreme example is a noncompliant pd that provides the proper signature during detection but then behaves like a low valued resistor, say 50 ? , in parallel with a 1 f capacitor. when the pse has charged this noncompliant pd up to 20v, the 50 ? resistor will draw 400ma (the minimum ieee prescribed i lim current limit) keeping the port voltage at 20v for the remainder of t start . the external mosfet sees 24v to 37v v ds at 400ma to 450ma, dissipating 9.6w to 16.7w for 60ms (typ). the ltc4259a implements foldback to reduce the current limit when the mosfet v ds is high; see the foldback section. without foldback, the mosfet could see as much as 25.7w for 60ms (typ) when powering a shorted or a 250ns/div 4258 g04 gnd port voltage 20v/div gate voltage 10v/div port current 20a/div v ee +15v v dd = 3.3v v ee = C48v v ee v ee 0ma short applied fet off fast pull-down activated 100 s/div 4258 g05 port voltage 20v/div gate voltage 10v/div port current 500ma/div v dd = 3.3v v ee = C48v v ee v ee gnd 0ma current limit short applied short removed fast pull-down v ee +15v figure 15. rapid response to 1 ? short figure 16. rapid response to momentary 100 ? short
ltc4259a 20 4259afb applicatio s i for atio wu uu noncompliant pd with only a few ohms of resistance. with foldback, the mosfet sees a maximum of 18w for the duration of t start . the ltc4259as duty cycle protection enforces 15 times longer off time than on time, preventing successive at- tempts to power a defective pd from damaging the mosfet. system software can enforce even longer wait times. when the ltc4259a is operated in semiauto or manual modedescribed in more detail under operating modesit will not power on a port until commanded to do so by the host controller. by keeping track of t start and t icut faults, the host controller can delay turning on the port again after one of these faults even if the ltc4259a reports a detect good. in this way the host controller implements a mosfet cooling off period which may be programmed to protect smaller mosfets from repeated thermal cycling. the ltc4259a has built-in duty cycle protection for t icut and t start (see t icut timing and t start timing sections) that is sufficient to protect the mosfets shown in figure 1. before designing a mosfet into your system, carefully compare its safe operating area (soa) with the worst case conditions (like powering up a defective pd) the device will face. using transient suppressors, polyfuses and ex- tended wait times after disconnecting a pd are effective strategies to reduce the extremes applied to the external mosfets. surge suppressors and circuit protection ieee 802.3af power over ethernet is a challenging hot swap application because it must survive the (probably unin- tentional) abuse of everyone in the building. while hot swapping boards in a networking or telecom card cage is done by a trained technician or network administrator, anyone in the building can plug a device into the network. moreover, in a card cage the physical domain being pow- ered is confined to the card cage. with power over ether- net, the pse supplies power to devices up to 100 meters away. ethernet cables could potentially be cut, shorted together, and so on by all kinds of events from a contrac- tor cutting into walls to someone carelessly sticking a screwdriver where it doesnt belong. consequently, the power over ethernet power source (pse) must be designed to handle these events. the most dramatic of these is shorting a powered port. what the pse sees depends on how much cat-5 cable is between it and the short. if the short occurs on the far end of a long cable, the cable inductance will prevent the cur- rent in the cable from increasing too quickly and the ltc4259as built-in short-circuit protection will take con- trol of the situation and turn off the port. some energy is stored in the cable, but the transient suppressor on the port clamps the port voltage when the cable inductance causes the voltage to fly back after the mosfet is turned off. because the cable only had 600ma or so going through it, an smaj58a or equivalent device can easily control the port voltage during flyback. with no cable connected at all, a powered port shorted at the pses rj-45 connector can reach high current levels before the port is shut down. there is no cable inductance to store energy so once the port is shut down the situation is under control. a shorthence low inductancepiece of cat-5 will not limit the rapid increase of current when the port is shorted. even though the ltc4259a short-circuit shutdown is fast, the cable may have many amps flowing through it before the mosfet can be turned off. due to the high current, this short piece of cable flies back with significant energy behind it and must be controlled by the transient suppres- sor. choosing a surge suppressor that will not develop more than a few volts of forward voltage while passing more than 10a is important. a positive port voltage may forward bias the detect diode (d det n ), bringing the ltc4259as detect n pin positive as well and engaging the detect n clamps. this will generally not damage the ltc4259a but extreme cases can cause the ltc4259a to reset. when it resets, the ltc4259a signals an interrupt, alerting the host con troller which can then return the ltc4259a to normal operating mode. a substantial transient surge suppressor can typically protect the ltc4259a and the rest of the pse from these faults. placing a polyfuse between the rj-45 connector and the ltc4259a and its associated circuitry can provide additional protection. to meet safety requirements, place the polyfuse in the ground leg of the pses output. dc disconnect dc disconnect monitors the sense resistor voltage when- ever the power is on to make sure that the pd is drawing
ltc4259a 21 4259afb the minimum specified current. the disconnect timer counts up whenever port current is below 7.5ma (typ). if the t dis timer runs out, the corresponding port will be turned off and the disconnect bit in the fault register will be set. if the undercurrent condition goes away before the t dis timer runs out, the timer will reset. the timer will start counting from the beginning if the under current condition occurs again. the undercurrent circuit includes a glitch filter to filter out noise. the dc disconnect feature can be disabled by clearing the corresponding dc discon enable bits in the disconnect register (13h). the t dis timer duration can be programmed by bits 1 and 0 of register 16h. the ltc4259a implements a variety of current sense and limit thresholds to control current flowing through the port. figure 17 is a graphical representation of these thresholds and the action the ltc4259a takes when currrent crosses the thresholds. counts to t dis , the port is turned off and the ports discon- nect bit in the fault register is set. if the impedance falls (ac current rises above i acdmin ) before the maximum count of the disconnect timer, the timer resets and the port remains powered. like dc disconnect, ac disconnect can also be disabled by clearing the corresponding ac discon enable bits in the disconnect register (13h). ac disconnect is also affected by the t dis duration programmed in register 16h. unlike dc disconnect, ac disconnect has no continuous time output to the timer. rather, ac disconnect will reset the timer once every cycle, 1/f oscin , of the oscin signal if the port draws more than i acdmin during that period. because of this behavior, the time to turn off the port after pd removal, t dis , may vary by up to one cycle of oscin (1/f oscin ) from the delay programmed with the t dis1 and t dis0 bits. note that ac disconnect and dc disconnect signals that reset the t dis timer are ored together. thus on a port where both disconnect modes are enabled, either disconnect sensing method can keep the port powered even if the other reports that there is no pd connected. the ac disconnect circuitry senses the port and power over ethernet connection from the detect pins. connect a 0.47 f 100v x7r capacitor (c det ) and a 1k resistor (r det ) from the ports detect pin to the ports output as shown in figure 18. this provides an ac path for sensing the port impedance. the 1k resistor, r det , limits current flowing through this path during port power on and power off. sizing of capacitors is critical to ensure proper function of ac disconnect. c pse (figure 18) controls the connection impedance on the pse side. its capacitance must be kept low enough for ac disconnect to be able to sense the pd. for operation near 100hz, use a c pse of 0.1 f. on the other hand, c det has to be large enough to pass the signal at the frequency of oscin. for f oscin 100hz, use at least a 0.47 f 100v x7r capacitor. the sizes of c pse , c det , r det and the frequency, f oscin , are chosen to create an economical, physically compact and functionally ro bust system. moreover, the complete power over ether- net ac disconnect system (pse, transformers, cabling, pd, etc.) is complex; deviating from the recommended applicatio s i for atio wu uu figure 17. ltc4259a current sense and limits 0ma 0mv 100ma current r s = 0.5 ? dc dis- connect cut (i cut ) limit (i lim ) short circuit effect sense n voltage 50mv 200ma 100mv 300ma 150mv 400ma 200mv 500ma 250mv 600ma 300mv current limit port off in t icut or t start current limit in 1 s normal operation port off in t dis 4259a f17 ac disconnect ac disconnect is an alternate method of sensing the pres- ence or absence of a pd by monitoring the port impedance. the ltc4259a forces a signal, amplified from the oscin pin, out of the detect pins and onto the power over eth- ernet connection. it calculates the connection impedance from ohms law, z port = v ac /i ac . like dc disconnect, the ac disconnect sensing circuitry controls the disconnect timer. when the connection impedance rises (ac current falls below i acdmin ) due to the removal of the pd, the dis- connect timer counts up. if the impedance remains high (ac current remains below i acdmin ), the disconnect timer
ltc4259a 22 4259afb values of c det , r det and c pse is discouraged. contact the ltc applications department for additional support. when choosing c det and c pse , carefully consider voltage derating of the capacitors. capacitors built around an x7r dielectric will have about 60% of the specified capacitance at their rated voltage. operated at half their rated voltage, x7r capacitors exhibit more than 80% of their specified capacitance. with other ceramic dielectrics commonly used in 50v and 100v chip capacitors, capacitance falls much more dramatically with voltage. at their rated volt- age, y5v or z5u capacitors exhibit less than 30% of their zero-bias capacitance. ceramic capacitors can also have significantly less capacitance at elevated temperatures. in order to produce the desired capacitance at the operating bias, 100v or 250v x7r capacitors should be used with the ltc4259a. as illustrated in figure 19, the power over ethernet con- nection between the pse and pd includes a large amount of capacitance. cable capacitance is particularly troubling because cat-3 and cat-5 pair-to-pair capacitance is not tightly specified by the ieee 802.3 standard or well con- trolled by cable manufacturers. considering that patch panels, additional connectors, old wiring, etc. are likely to be placed between the pse and pd, pair-to-pair capaci- tance is a pretty nebulous quantity. consequently, the cables contribution to the port impedance (at the fre- quency used for ac disconnect) can be a concern. assumimg that f oscin is 100hz, the 0.1 f of c pse plus 0.05 f of cable capacitance gives a port impedance of 10k at 100hz. the pd ac signature resistance is about 25k. connecting a pd with the maximum allowed resistance of 26.25k brings the connection impedance to about 8k. the presence of a pd only makes a 20% reduction in the port impedance requiring the ac disconnect circuitry to be quite sensitive. when the oscin pin is driven with a sine wave, the ltc4259a is able to distinguish between capaci- tive impedance and resistive impedance on the power over ethernet connection. ac disconnect is reliable for cable capacitance up to about 0.2 f, nearly an order of magni- tude greater than worst case for a long cat-3 or cat-5 cable. applicatio s i for atio wu uu figure 18. ac disconnect single port application circuit (port 4 shown) figure 19. simplified ac disconnect circuit with impedances at 100hz level shift detect4 agnd dgnd oscin 1/4 ltc4259a C48v gnd out4 r out4 10k r s4 0.5 ? 1% d det4 cmpd3003 pd r det4 1k r pd_d 26.25k c pd_d 0.05 f c det4 0.47 f 100v x7r c pse4 0.1 f 100v x7r 4259a f18 d ac4 s1b q4 gate4 sense4 v ee oscillator input current sense r det 1k z link < 14k z cable < 32k pd ~16k ~7k z pd < 14k c det 0.47 f c pse 0.10 f c cable 0.05 f <32k c pd_d 0.05 fr pd_d < 26.25k 4259a f19
ltc4259a 23 4259afb oscin input and oscillator requirements ac disconnect depends on an external oscillator source applied to the oscin pin. the ltc4259a measures port impedance by applying an amplified version of the oscin signal to the ports detect pin (see figure 18). the oscillator should be well-controlled because errors in this signal become errors in the measured port impedance. as shown in figure 19, the load being sensed by ac discon- nect has a resistive and a large reactive component. current through the pds signature resistor depends on the amplitude of the ac signal while current into the capacitors depends on the slew rated: i = c ? dv/dt. consequently, the ltc4259a is sensitive to the amplitude and slew rate of the oscin signal, but is more tolerant of frequency and offset errors. internal limits prevent the ltc4259a from being adversely affected by oscin sig- nals with excessive amplitude. there are many ways to build oscillators with controlled amplitudes and slew rates, especially since the frequency of the oscillator does not have to be well-controlled. contact the ltc applications department for oscillator circuits. as alluded to previously, ac disconnect is complicated and redesigning for different component sizes is a difficult task. for optimum performance, use the recommended component values and drive oscin with a 100hz 2v p-p , 1.2v offset sine wave. keep in mind that the ieee 802.3af specification places upper limits of 100v/ms on the slew rate and 500hz on the frequency of the ac signal at the port. voltage gain, a vacd , from oscin to detect n in- creases the slew rate by the voltage gain. since a vacd has a maximum absolute value of 3.3v/v ( 3v typ), the slew rate at the oscin pin must be less than 30v/ms. a slew rate around 0.6v/ms at oscin will work with the recom- mended values of c det , r det and c pse . the ltc4259as oscin input amplifier will accept signals between dgnd C 0.3v and v dd + 0.5v. this amplifier has a gain of C1 and is referenced to 1.2v above dgnd. an oscin voltage greater than 2.2v will cause the amplifiers output to clip against dgnd. clipping will not affect the performance of ac disconnect until the clipping becomes so severe that even the midrange (where the controlled slew rate occurs) of the signal is clipped. keep the midrange or average voltage of the oscin signal between 0.9v and 1.5v to avoid severe clipping. oscin signals below dgnd can interact with the esd protection circuitry on the pin and are not recommended. also, meeting the ieee 802.3af specification for maximum ac amplitude on the port just after the pd is removed depends on the oscin input peak- to-peak amplitude. clipping by ltc4259as oscin input circuitry will generally ensure that this specification is not exceeded. note that under normal operation, the ac dis- connect output on the detect n pin will have an amplitude near 6v peak-to-peak. the combination of r det , c det and c pse attenuate the signal so roughly half this amplitude is seen at the port when the port is powered and the pd has just been removed. when the pd is still connected there will be almost no ac signal at the port. the ltc4259a monitors pin 36 for the presence of an oscillating signal. if no signal is present and the osc fail mask bit is set, then osc fail (bit 1 of the supply event register) is set, triggering an interrupt. as the ltc4259as ac disconnect circuitry self-checks the oscin signal, the osc fail bit is intended as a fault indicator to alert the pse host controller. the osc fail bit has no effect beyond triggering the interrupt. a clear osc fail bit indicates that the oscin signal goes below 0.6v and above 1.8v at least once every 250ms. it does not necessarily guarantee that ac disconnect will function properly. however, ac discon- nect itself is a more thorough test of the oscin signal. when the oscin signal is either absent or corrupted, powered ports with ac disconnect enabled (and dc dis- connect not enabled) will automatically disconnect. after the ltc4259a is reset (by power on, reset all bit or the reset pin) the osc fail bit is set. once the osc fail bit is cleared, it will only be set by an invalid signal on the oscin pin or another reset. serial digital interface the ltc4259a communicates with a host (master) using the standard 2-wire interface as described in the smbus specification version 2.0 (available at http://smbus.org). the smbus is an extension of the i 2 c bus, and the ltc4259a is also compatible with the i 2 c bus standard. the timing diagrams (figures 6 through 10) show the timing relationship of the signals on the bus. the two bus applicatio s i for atio wu uu
ltc4259a 24 4259afb applicatio s i for atio wu uu lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources, such as the ltc1694 smbus accelerator, are required on these lines. if the sda and scl pull-ups are absent, not con- nected to the same positive supply as the ltc4259as v dd pin, or are not activated when the power is applied to the ltc4259a, it is possible for the ltc4259a to see a start condition on the i 2 c bus. the interrupt pin (int) is only updated between i 2 c transactions. therefore if the ltc4259a sees a start condition when it powers up because the scl and sda lines were left floating, it will not assert an interrupt (pull int low) until it sees a stop condition on the bus. in a typical application the i 2 c bus will immediately have traffic and the ltc4259a will see a stop so soon after power up that this momentary condi- tion will go unnoticed. isolating the serial digital interface ieee 802.3af requires that network segments be electri- cally isolated from the chassis ground of each network interface device. however, the network segments are not required to be isolated from each other provided that the segments are connected to devices residing within a single building on a single power distribution system. for simple devices such as small powered ethernet switches, the requirement can be met by using an iso- lated power supply to power the entire device. this implementation can only be used if the device has no electrically conducting ports other than twisted-pair eth- ernet. in this case, the sdain and sdaout pins of the ltc4259a can be connected together to act as a standard i 2 c/smbus sda pin. if the device is part of a larger system, contains serial ports, or must be referenced to protective ground for some other reason, the power over ethernet subsystem including the ltc4259as must be electrically isolated from the rest of the system. the ltc4259a includes separate pins (sdain and sdaout) for the input and output functions of the bidirectional data line. this eases the use of optocouplers to isolate the data path between the ltc4259as and the system controller. figure 20 shows one possible implementation of an isolated inter- face. the sdaout pin of the ltc4259a is designed to drive the inputs of an optocoupler directly, but a standard i 2 c device typically cannot. u1 is used to buffer i 2 c signals into the optocouplers from the system controller side. schmitt triggers must be used to prevent extra edges on transitions of sda and scl. bus addresses and protocols the ltc4259a is a read-write slave device. the master can communicate with the ltc4259a using the write byte, read byte and receive byte protocols. the ltc4259as primary serial bus address is (010a 3 a 2 a 1 a 0 )b, as designated by pins ad3-ad0. all ltc4259as also respond to the address (0110000)b, allowing the host to write the same command into all of the ltc4259as on a bus in a single transaction. if the ltc4259a is asserting (pulling low) the int pin, it will also acknowledge the alert response address (0001100)b using the receive byte protocol. the start and stop conditions when the bus is idle, both scl and sda must be high. a bus master (typically the host controller) signals the beginning of communication with a slave device (like the ltc4259a) by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. a repeated start condition is functionally the same as a start condition, but used to extend the protocol for a change in data transmission direction. a stop condition is not used to set up a repeated start condition, for this would clear any data already latched in. when the master has finished commu- nicating with the slave, it issues a stop condition. a stop condition is generated by transitioning sda from low to high while scl is high. the bus is then free for communi- cation with another smbus or i 2 c device. acknowledge the acknowledge signal is used for handshaking between the master and the slave. an acknowledge (active low) generated by the slave lets the master know that the latest byte of information was received. the corresponding scl clock pulse is always generated by the master. the master releases the sda line (high) during the acknowledge
ltc4259a 25 4259afb figure 20. optoisolating the i 2 c bus applicatio s i for atio wu uu 4258a f20 v dd int scl sdain sdaout ad0 ad1 ad2 ad3 dgnd agnd ltc4259a byp v dd int scl sdain sdaout ad0 ad1 ad2 ad3 dgnd agnd ltc4259a v dd int scl sdain sdaout ad0 ad1 ad2 ad3 dgnd agnd ltc4259a v dd int scl sdain sdaout ad0 ad1 ad2 ad3 dgnd agnd ltc4259a v dd int scl sdain sdaout ad0 ad1 ad2 ad3 dgnd agnd ltc4259a ? ? ? 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f + 10 f 2k 2k 0.1 f 0.1 f 0.1 f byp 0.1 f byp 0.1 f byp 0.1 f byp 0.1 f 200 ? 200 ? 200 ? 200 ? u2 u3 u1 hcpl-063l hcpl-063l v dd cpu scl sda smbalert gnd cpu u1: fairchild nc7wz17 u2, u3: agilent hcpl-063l to controller isolated 3.3v isolated gnd 0100000 0100001 0100010 0101110 0101111 i 2 c address
ltc4259a 26 4259afb clock pulse. the slave must pull down the sda line during the acknowledge clock pulse so that it remains a stable low during the high period of this clock pulse. when the master is reading from a slave device, it is the masters responsibility to acknowledge receipt of the data byte in the bit that follows unless the transaction is complete. in that case the master will decline to acknowledge and issue the stop condition to terminate the communication. write byte protocol the master initiates communication to the ltc4259a with a start condition and a 7-bit bus address followed by the write bit (wr) = 0. if the ltc4259a recognizes its own address, it acknowledges and the master delivers the com- mand byte, signifying to which internal ltc4259a register the master wishes to write. the ltc4259a acknowl edges and latches the lower five bits of the command byte into its register address register. only the lower five bits of the command byte are checked by the ltc4259a; the upper three bits are ignored. the master then delivers the data byte. the ltc4259a acknowledges once more and latches the data into the appropriate control register. finally, the master terminates the communication with a stop condi- tion. upon reception of the stop condition, the register address register is cleared (see figure 7). read byte protocol the master initiates communication from the ltc4259a with a start condition and the same 7-bit bus address followed by the write bit (wr) = 0. if the ltc4259a recognizes its own address, it acknowledges and the master delivers the command byte, signifying which internal ltc4259a register it wishes to read from. the ltc4259a acknowledges and latches the lower five bits of the command byte into its register address register. at this time the master sends a repeated start condition and the same 7-bit bus address followed by the read bit (rd) = 1. the ltc4259a acknowledges and sends the contents of the requested register. finally, the master declines to acknowledge and terminates communication with a stop condition. upon reception of the stop condition, the register address register is cleared (see figure 8). receive byte protocol since the ltc4259a clears the register address register on each stop condition, the interrupt register (register 0) may be read with the receive byte protocol as well as with the read byte protocol. in this protocol, the master initiates communication with the ltc4259a with a start condition and a 7-bit bus address followed by the read bit (rd) = 1. the ltc4259a acknowledges and sends the contents of the interrupt register. the master then de- clines to acknowledge and terminates communication with a stop condition (see figure 9). alert response address and the int pin in a system where several ltc4259as share a common int line, the master can use the alert response address (ara) to determine which ltc4259a initiated the interrupt. the master initiates the ara procedure with a start condition and the 7-bit ara bus address (0001100)b followed by the read bit (rd) = 1. if an ltc4259a is asserting the int pin, it acknowledges and sends its 7-bit bus address (010a 3 a 2 a 1 a 0 )b and a 1 (see figure 10). while it is sending its address, it monitors the sdain pin to see if another device is sending an address at the same time using standard i 2 c bus arbitration. if the ltc4259a is sending a 1 and reads a 0 on the sdain pin on the rising edge of scl, it assumes another device with a lower address is sending and the ltc4259a immediately aborts its transfer and waits for the next ara cycle to try again. if transfer is successfully completed, the ltc4259a will stop pulling down the int pin. when the int pin is released in this way or if a 1 is written into the clear interrupt pin bit (bit 6 of register 1ah), the condition causing the ltc4259a to pull the int pin down must be removed before the ltc4259a will be able to pull int down again. this can be done by reading and clearing the event registers or by writing a 1 into the clear all interrupts bit (bit 7 of register 1ah). the state of the int pin can only change between i 2 c transactions, so an interrupt is cleared or new interrupts are generated after a transaction completes and before new i 2 c bus communication commences. periodic polling of the alert response address can be used instead of the int pin if desired. if any device acknowledges the alert response address, then the int line, if connected, would have been low. applicatio s i for atio wu uu
ltc4259a 27 4259afb system software strategy control of the ltc4259a hinges on one decision, the ltc4259as operating mode. the three choices are de- scribed under operating modes. in auto mode the ltc4259a can operate autonomously without direction from a host controller. because ltc4259as running in auto mode will power every valid pd connected to them, the pse must have 15.4w/port available. to reduce the power requirements of the C48v supply, pse systems can track power usage, only turning on ports when sufficient power is available. the ieee describes this as a power allocation algorithm and places two limitations: the pse shall not power a pd unless it can supply the guaranteed power for that pds class (see table 2) and power allocation may not be based solely on a history of each pds power consumption. in order for a pse to implement power allocation, the pses processor/con- troller must control whether ports are poweredthe ltc4259a cannot be allowed to operate in auto mode. semiauto mode fits the bill as the ltc4259a automati- cally detects and classifies pds, then makes this informa- tion available to the host controller, which decides to apply power or not. operating the ltc4259a in manual mode also lets the controller decide whether to power the ports but the controller must also control detection and classification. if the host controller operates near the limit of its computing resources, it may not be able to guide a manual mode ltc4259a through detect, class and port turn-on in less than the ieee mandated maximum of 950ms. in a typical pse, the ltc4259as will operate in semiauto mode as this allows the controller to decide to power a port without unduly burdening the controller. with an interrupt mask of f4h, the ltc4259a will signal to the host after it has successfully detected and classed a pd, at which point the host can decide whether enough power is available and command the ltc4259a to turn that port on. similarly, the ltc4259a will generate interrupts when a ports power is turned off. by reading the ltc4259as interrupt register, the host can determine if a port was turned off due to overcurrent (t start or t icut faults) or because the pd was removed (disconnect event). the host then updates the amount of available power to reflect applicatio s i for atio wu uu the power no longer consumed by the disconnected pd. setting the msb of the interrupt mask causes the ltc4259a to communicate fault conditions caused by failures within the pse, so the host does not need to poll to check that the ltc4259as are operating properly. this interrupt driven system architecture provides the controller with the final say on powering ports at the same time, minimizing the controllers computation requirements because inter- rupts are only generated when a pd is detected or on a fault condition. the ltc4259a can also be used to power older powered ethernet devices that are not 802.3af compliant and may be detected with other methods. although the ltc4259a does not implement these older detection methods auto- matically, if software or external circuitry can detect the noncompliant devices, the host controller may command the ltc4259a to power the port, bypassing ieee compli- ant detection and classification and sending power to the noncompliant device. logic level supply in additon to the 48v used to source power to each port, a logic level supply is required to power the digital portion of the ltc4259a. to simplify design and meet voltage isolation requirements, the logic level supply can be generated from the isolated C 48v supply. figure 21 shows an example method using an lt ? 1619 to control a C48v to 3.3v current mode supply. this boost con- verter topology uses the lt1619 current mode controller and a current mirror which reflects the 3.3v output voltage to the C48v rail, improving the regulation toler- ance over the more traditional large resistor voltage divider. this approach achieves high accuracy with a transformerless design. ieee 802.3af compliance and external component selection the ltc4259a is designed to control power delivery in ieee 802.3af compliant power sourcing equipment (pse). because proper operation of the ltc4259a may depend on external signals and power sources, like the C48v supply (v ee ) or the oscin oscillator source, external
ltc4259a 28 4259afb components such as the sense resistors (r s ), and possi- bly software running on an external microprocessor, using the ltc4259a in a pse does not guarantee 802.3af compliance. using an ltc4259a does get you most of the way there. this section discusses the rest of the elements that go along with the ltc4259a to make an 802.3af complaint pse. each paragraph below addresses a com- ponent which is critical for pse compliance as well as possible pitfalls that can cause a pse to be noncompliant. for further assistance please contact linear technologys applications department. sense resistors the ltc4259a is designed to use a 0.5 ? sense resistor, r s , to monitor the current through each port. the value of the sense resistor has been minimized in order to reduce power loss and as a consequence, the voltage which the ltc4259a must measure is small. each port may be drawing up to 450ma with this current flowing through the sense resistor and associated circuit board traces. to prevent parasitic resistance on the circuit board from obscuring the voltage drop across the sense resistor, the ltc4259a must kelvin sense the resistor voltage. one way to achieve kelvin sensing is star grounding, shown pictorially in figure 1. another option is to use a C 48v power plane to connect the sense resistor and the ltc4259a v ee pin. either of these strategies will prevent voltages developed across parasitic circuit board resis- tances from affecting the ltc4259a current measure- ment accuracy. the precision of the sense resistor directly affects the measurement of the ieee parameters i inrush , i lim , i cut and i min . therefore, to maintain ieee compli- ance, use a resistor with 0.5% or better accuracy. power mosfets the ltc4259a controls power mosfets in order to regulate current flow through the ethernet ports. under certain conditions these mosfets have to dissipate sig- nificant power. see the choosing external mosfets sec- tion for a detailed discussion of the requirements these devices must meet. common mode chokes both nonpowered and powered ethernet connections achieve best performance (for data transfer, power trans- fer and emi) when a common mode choke is used on each port. in the name of cost reduction, some designs share a common mode choke between two adjacent ports. even for nonpowered ethernet, sharing a choke is not recom- mended. with two ports passing through the choke, it cannot limit the common mode current of either port. instead, the choke only controls the sum of both ports common mode current. because cabling from the ports generally connects to different devices up to 200m apart, applicatio s i for atio wu uu drv 100 ? 100 h 4.7 h b1100 10 f 16v 4700pf 100pf cmpz4702b isolated gnd isolated C48v si2328ds fmmt593 fmmt593 876 5 2 3 4 1 gate v in v c s/s sense lt1619 fb gnd si2328ds 510 ? 47k 3.32k 1% 0.100 ? 1% 1w 1.24k 1% 100k 4259a f21 910k 1 f 100v + v ee 10 ? 47 f 10v v dd 3.3v 300ma + 47 f 10v isolated gnd + figure 21. 48v to 3.3v boost converter
ltc4259a 29 4259afb applicatio s i for atio wu uu a current loop can form. in such a loop, common mode current flows in one port and out the other, and the choke will not prevent this because the sum of the currents is zero. another way to view this interaction between the paired ports is that the choke acts as a transformer coupling the ports common modes together. in nonpowered ethernet, common mode current results from nonidealities like ground loops; it is not part of normal operation. however, power over ethernet sends power and hence significant current through the ports; common mode current is a byproduct of normal opera- tion. as described in the choosing external mosfets section and under the power supplies heading below, large transients can occur when a ports power is turned on or off. when a powered port is shorted (see surge suppressors and circuit protection), a ports common mode current may be excessive. sharing a common mode choke between two ports couples start-up, disconnect and fault transients from one port to the other. the end result can range from momentary noncompliance with 802.3af to intermittent behavior and even to excessive voltages that may damage circuitry (in both the pse and pd) connected to the ports. detect, ac blocking and transient suppressor diodes during detection and classification, the ltc4259a senses the port voltage through the detect diodes d det in fig- ure 18. excessive voltage drop across d det will corrupt the ltc4259as detect and classification results. select a diode for d det that will have less than 0.7v of forward drop at 0.4ma and less than 0.9v of forward drop at 50ma. when the port is powered, the detect diode is reverse bi- ased. any leakage through the detect diode prevents the ltc4259a from sensing all the current coupled through the c det capacitor. at high temperature with 70v of reverse bias, a typical switching diode like the 1n4148 may have more than 50 a of leakage. such leakage can interfere with ac disconnect because it is a large fraction of the ltc4259as i acdmin threshold. using a low leakage detect diode like the cmpd3003 is recommended. the ac blocking diodes can interfere with ac disconnect sensing if they become leaky. if the ac blocking diode (d ac in figure 18) begins leaking, it contributes to the ethernet port impedance, potentially bringing the impedance low enough to draw i acdmin from the detect pin and keep the port powered. more likely, leakage through the ac block- ing diode will cause shifts in the ac disconnect threshold that are not large enough to make the pse noncompliant. generally, diode leakage is caused by voltage or tempera- ture stress. diodes that are rated to 100v or more and can handle dissipating at least 0.5w should be acceptable in this application. other component leakages can have a similar affect on ac disconnect and even affect dc discon- nect if the leakage becomes severe. among components to be wary of are the transient surge suppressors. the devices shown in figure 1 are rated for less than 5 a of leakage at 58v. however there is a potential for stress induced leakage, so healthy margins should be used when selecting diodes for these applications. capacitors sizing of both the c det and c pse capacitors is critical to proper operation of the ltc4259as ac disconnect sens- ing. see the ac disconnect section for more information. also, c pse may be important to the voltage stability of a powered port. port voltage instability is generally not a problem if v ee , the C48v supply, is well bypassed. for both of these reasons be aware that many ceramic dielectrics have dramatic dc voltage and temperature coefficients. a 0.22 f ceramic capacitor is often nowhere near 0.22 f when operating at 50vdc or 100vdc. use 100v or higher rated x7r capacitors for c det and c pse as these have re- duced voltage dependance while also being relatively small and inexpensive. power supplies the ltc4259a must be supplied with 3.3v (v dd ) and C48v (v ee ). poor regulation on either of these supplies can lead to noncompliance. the ieee requires a pse output voltage between 44v and 57v. when the ltc4259a begins powering an ethernet port, it controls the current through the port to minimize disturbances on v ee . how- ever, if the v ee supply is underdamped or otherwise unstable, its voltage could go outside of the ieee specified limits, causing all ports in the pse to be noncompliant. this scenario can be even worse when a pd is unplugged because the current can drop immediately to zero. in both
ltc4259a 30 4259afb cases the port voltage must always stay between C44v and C57v. in addition, the 802.3af specification places specific ripple, noise and load regulation requirements on the pse. among other things, disturbances on either v dd or v ee can adversely affect detection, classification and the ac disconnection sensing. proper bypassing and stability of the v dd and v ee supplies is important. another problem that can affect the v ee supply is insuffi- cient power, leading to the supply voltage drooping out of the specified range. the 802.3af specification states that if a pse powers a pd it must be able to provide the maximum power level requested by the pd based on the pds classification. the specification does allow a pse to choose not to power a port because the pd requires more power than the pse has left to deliver. if a pse is built with a v ee supply capable of less than 15.4w ? (number of pses ethernet ports), it must implement a power alloca- tion algorithm that prevents ports from being powered when there is insufficient power. because the specifica- tion also requires the pse to supply 400ma at up to a 5% duty cycle, the v ee supply capability should be at least a few percent more than the maximum total power the pse will supply to pds. finally, the ltc4259as draw current from v ee . if the v dd supply is generated from v ee , that applicatio s i for atio wu uu power divided by the switcher efficiency must also be added to the v ee supplys capability. fast v ee transients can damage the ltc4259a. limit the v ee slew rate to 50mv/ s. in most applications, existing v ee bypass capacitors (described above) will cause the v ee supply to slew much slower than 50mv/ s. oscin input ac disconnect also relies on an oscillating signal applied to the oscin pin. requirements for this signal are pro- vided in the oscin input and oscillator requirements section. out-of-band noise on the oscin pin will disrupt the ltc4259as ability to sense the absence of a pd. any noise present at the oscin pin is amplified by the ltc4259a and driven out of the detect pins (of powered ports with ac disconnect enabled). due to the amount of capacitance connected to the detect pins, driving this noise can easily require more than i acdmin , tripping the detect pin current sense and keeping the port powered. during circuit board layout, keep wiring from the oscillator to the oscin pin away from noise sources like digital clock and data lines. a single-stage rc lowpass filter (shown in figure 22) will attenuate out-of-band noise.
ltc4259a 31 4259afb u package descriptio gw package 36-lead plastic ssop (wide .300 inch) (reference ltc dwg # 05-08-1642) gw36 ssop 0502 0 C 8 typ 0.231 C 0.3175 (.0091 C .0125) 0.610 C 1.016 (.024 C .040) 7.417 C 7.595** (.292 C .299) 45 0.254 C 0.406 (.010 C .016) 2.286 C 2.387 (.090 C .094) 0.127 C 0.305 (.005 C .0115) 2.463 C 2.641 (.097 C .104) 0.800 (.0315) bsc 0.304 C 0.431 (.012 C .017) 15.290 C 15.544* (.602 C .612) 1 2 3 4 5 6 7 8 9 101112131415161718 10.160 C 10.414 (.400 C .410) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 10.668 min recommended solder pad layout 7.416 C 7.747 0.800 typ 0.520 0.0635 1.143 0.127 dimension does not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side * dimension does not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side ** millimeters (inches) note: 1. controlling dimension: millimeters 2. dimensions are in information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ltc4259a 32 4259afb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt 1205 rev b ? printed in usa related parts part number description comments lt1619 low voltage current mode pwm controller C48v to 3.3v at 300ma, msop package ltc1694 smbus/i 2 c accelerator improved i 2 c rise time, ensures data integrity ltc4255 quad network power controller non-ieee 802.3af compliant current levels ltc4257 ieee 802.3af pd interface controller 100v, 400ma internal switch, programmable class ltc4257-1 ieee 802.3af pd interface controller 100v, 400ma internal switch, dual current limit, programmable class ltc4258 quad ieee 802.3af power over ethernet controller dc disconnect only ltc4267 ieee802.3af pd interface with 100v, 400ma uvlo switch, dual inrush current, programmable class integrated switching regulator 4258 f22a 1 2 3 4 5 6 7 8 2k 2k 0.1 f 0.1 f 0.1 f 200 ? 200 ? 200 ? 200 ? u2 u3 u1 hcpl-063l hcpl-063l v dd cpu scl sda smbalert gnd cpu d ac : diodes inc or fairchild s1b d det : central semi cmpd3003 d tss : diodes inc smaj58a c det : tdk c3225x7r2a474k l1: pulse eng po473 q1: fairchild irfm120a r s : vishay wsl2010 0.5 ? 0.5% t1: pulse eng h2009 u1: fairchild nc7wz17 u2, u3: agilent hcpl-063l to controller phy (network physical layer chip) d tss 58v smaj58a 0.1 f 100v x7r 1 f 1k v ee sense gate out v dd scl sdain sdaout int d det cmpd3003 10k d ac s1b r det 1k 0.1 f 100v x7r l1 c det 0.47 f 100v x7r r s 0.5 ? q1 irfm120a 1/4 ltc4259a dgnd oscin agnd detect byp C48v isolated isolated 3.3v isolated gnd 2v p-p , 100hz 1.2v offset oscillator 0.01 f 200v 0.01 f 200v 0.01 f 200v 0.01 f 200v 75 ? 75 ? 75 ? 75 ? rj45 connector 1/2 pulse h2009 t1 1:1 t1 1:1 1000pf 2000v figure 22. one complete isolated powered ethernet port typical applicatio u

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